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? astec semiconductor features size (single tile) ? 87 x 75 mils expandability of array (to 2 or 4 tiles) component availability (single tile) ? small npn 48 ? dual collector pnp 21 ? vertical pnp 4 ? power npn 3 ? diffused resistors (total) ? 300 k w ? pinch resistors (3-terminal, 30k w )8 ? cross-unders 13 ? buses 6 basic electrical specs ? transistor matching (npn & pnp) <2% ? primary voltage limitations: lv ceo 18 v bv cbo 30 v ? diffusion to substrate (ground) 30 v ? npn parameters beta 80C500 f t (1ma) 300 mhz bv ebo 7 v ? pnp parameters: beta 20C300 f t (1ma) 300 mhz bv ebo 30 v AS17XX semicustom bipolar array description the AS17XX is astecs proprietary semicustom bipolar array. this semicustom ic is a collection of individual transistors and resistors in a fixed configuration. the custom circuit is manufactured by creating a single metal mask to connect the components. this allows the designer to deal with only one mask for the ic layout instead of the actual 10 mask process. the semicustom array is useful for a wide range of functions, both analog and digital. in its simplest configuration, the AS17XX has 76 active devices available, but can be ex- panded to give up to four times this number in its largest configuration. this expandability of the array is a unique feature, allowing a whole range of semicustom circuits to be manufactured. because astec has ongoing manufacturing of high volume circuits on this array, incremental wafer costs for engineering purposes are low. therefore quality and reliability can be maintained even with small volume or engineering lots. since the silicon can be completely processed and held awaiting only the metal etch and passivation steps, ex- tremely fast turn-around times can be achieved. the AS17XX bipolar array uses a standard 20 volt bipolar technology. although quite similar to industry standard ar- rays, it has a number of important improvements. first, the ratio of pnps to npns has been increased to allow for more modern design practice. second, the process has been modified to allow for a deep collector diffusion (sinker) which not only improves the v ce(sat) of the transistors, but also allows for the elimination of regions with thin oxide which historically plague semicustom die with electrostatic dis- charge reliability concerns. third, a set of low resistance sinker resistors allows for bussing supply or signal lines without using active components for cross-unders. in addi- tion, the specific component geometries have been further optimized to facilitate the layout compared to the industry standard arrays. resistors are now in a binary weighted 500 / 1k / 2k / 4k sequence for more simple value calcula- tions. the power devices use multiple standard size emitters 119
AS17XX semicustom bipolar array 120 astec semiconductor pin configuration top view pdip (n) as1700-npn kit part pdip (n) as1700-pnp kit part pdip (n) as1700-pwr kit part die configuration top view figure 1. single tile bipolar array so that they may also be used to create a device with an integral emitter area ratio with respect to a standard small npn. the AS17XX bipolar array can be packaged in industry standard dip or surface mount pack- ages with 8 to 40 leads. the number of pads available on the AS17XX varies with the number of tiles used as follows: single tile per die = 18 pads, two tiles per die = 30 pads, and four tiles per die = 40 pads. the extra pads not used for bonding to leads can be used for wafer level testing, trimming, and debugging. 14 13 c 12 b 11 e 10 c 9b 8 1 sub 2 c 3 b 4 e 5 c 6 b 7 ee v be 14 13 c 12 b 11 e 10 c 9b 8 1 sub 2 c 3 b 4 e 5 c 6 b 7 ee c 14 13 c 12 b 11 e 10 b 9b 8 1 sub 2 c 3 b 4 e 5 c 6 b 7 ee e
semicustom bipolar array AS17XX 121 astec semiconductor absolute maximum ratings parameter symbol rating unit continuous power dissipated at 25 cp d single transistor 300 mw total package 1400 mw junction temperature t j 150 c storage temperature t stg C 65 to 150 c lead temperature, soldering 10 seconds t l 300 c stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational se ctions of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. electrical characteristics all parameters measured at 25 c. parameter symbol test condition min typ max unit as1700-npn: minimum npn collector-to-emitter breakdown voltage lv ceo i c = 1 ma 20 35 v collector-to-base breakdown voltage bv cbo i c = 100 m a5060v emitter-to-base breakdown voltage bv ebo i e = 10 m a58v collector cutoff current i ceo v ce = 18 v 0 2 100 na collector-to-emitter saturation voltage v ce sat i b = 10 m a, i c = 100 m a 0 95 200 mv base-to-emitter voltage v be v ce = 3 v, i c = 100 m a 650 680 700 mv static forward current-transfer ratio b (h fe )v ce = 3 v, i c = 100 m a 80 125 500 early voltage v a C150 v transistor matching (measuring d i c )i c = 200 m a C10 <1 10 % as1700-pwr: large npn (20-emitter) collector-to-emitter breakdown voltage lv ceo i c = 1 ma 20 35 v collector-to-base breakdown voltage bv cbo i c = 100 m a5058v emitter-to-base breakdown voltage bv ebo i e = 10 m a 5 7.6 v collector cutoff current i ceo v ce = 18 v 0 2 100 na collector-to-emitter saturation voltage v ce sat i b = 200 m a, i c = 2 ma 0 20 200 mv base-to-emitter voltage v be v ce = 3 v, i c = 200 m a 650 680 700 mv static forward current-transfer ratio b (h fe )v ce = 3 v, i c = 2 ma 80 125 500 early voltage v a C150 v
AS17XX semicustom bipolar array 122 astec semiconductor electrical characteristics (contd) all parameters measured at 25 c. parameter symbol test condition min typ max unit as1700-pnp: lateral pnp collector-to-emitter breakdown voltage lv ceo i e = 100 m a3050v field-effect threshold voltage vtf i e = 10 m a36v p + to substrate leakage i sub i e = 100 m a, v b = 1 v 0 150 500 na collector cutoff current i ceo v ce = 18 v 0 2 100 na collector-to-emitter saturation voltage v ce sat i b = 10 m a, i e = 100 m a 0 150 200 mv base-to-emitter voltage v eb v ec = 3 v, i e = 100 m a 630 690 700 mv static forward current-transfer ratio b (h fe )v ec = 3 v, i e = 100 m a 20 60 300 early voltage v a C105 v transistor matching (measuring d i e )i e = 200 m a C10 <1 10 % double collector matching (meas. d i e )i e = 200 m a C10 <1 10 % as1700-pwr: vertical pnp collector-to-emitter breakdown voltage lv ceo i e = 100 m a3050v collector cutoff current i ceo v ce = 18 v 0 2 100 na collector-to-emitter saturation voltage v ce sat i b = 10 m a, i e = 100 m a 0 150 200 mv base-to-emitter voltage v eb v ec = 3 v, i e = 100 m a 650 680 700 mv static forward current-transfer ratio b (h fe )v ec = 3 v, i e = 100 m a 20 125 500
semicustom bipolar array AS17XX 123 astec semiconductor typical performance curves v ce sat vs i c over temperature (C 55 c to 125 c) v be sat vs i c over temperature (C 55 c to 125 c) current i c (ma) 0 v ce sat (mv) 200 500 450 400 350 300 150 100 50 250 0 2 4 6 8 101214161820 t = 125 c t = 25 c t = 0 c npn (small) forced beta: b = 10 t = 55 c t = 70 c current i c 10 m a 0 v be sat (mv) 200 500 900 1200 1400 100 m a 1 ma 10 ma 1300 1100 1000 800 600 400 300 100 700 t = 70 c t = 25 c t = 0 c t = 125 c t = 55 c npn (small) forced beta: b = 10 figure 21 figure 22 beta vs i c over temperature (C 55 c to 125 c) v ebo breakdown voltage vs temperature minimum npn figure 20 figure 19 current i c 10 m a 0 beta 40 100 140 200 260 300 100 m a 1 ma 10 ma 280 240 220 180 160 120 80 60 20 t = 50 c t = 70 c t = 100 c t = 125 c t = 55 c t = 25 c t = 0 c npn (small) v ce = 3 v t = 25 c temperature ( c) ?0 v ebo (v) 7 8 9 40 60 140 40 ?0 0 20 80 100 120 npn (small) i c = 10 m a
AS17XX semicustom bipolar array 124 astec semiconductor typical performance curves v be vs i c over temperature (C 55 c to 125 c) v be vs temperature with different i c beta vs i c over temperature (C 55 c to 125 c) v ebo breakdown voltage vs temperature temperature ( c) 0 v be (mv) 400 1000 900 800 700 600 300 200 100 500 60 40 20 0 20 40 60 80 100 120 140 i c = 10 ma i c = 1 m a i c = 10 m a i c = 100 m a i c = 1 ma i c = 5 ma v ce = 3 v npn (small) temperature ( c) ?0 v ebo (v) 7 8 9 40 60 140 40 20 0 20 80 100 120 npn (large) i c = 10 m a current i c 10 m a 0 beta 40 100 140 220 280 320 100 m a 1 ma 10 ma 300 260 240 200 180 120 80 60 20 t = 0 c v ce = 3 v 100 ma 160 t = 55 c t = 70 c t = 25 c t = 125 c npn (large) current i c 1 m a 300 v be (mv) 400 600 1100 1200 10 m a 1 ma 1000 900 800 700 500 100 m a 10 ma t = 125 c t = 0 c t = 25 c t = 70 c t = 55 c v ce = 3 v npn (small) figure 23 figure 24 figure 25 figure 26
semicustom bipolar array AS17XX 125 astec semiconductor typical performance curves v ce sat vs i c over temperature (C 55 c to 125 c) v be sat vs i c over temperature (C 55 c to 125 c) v be vs i c over temperature (C 55 c to 125 c) v be vs temperature with different i c temperature ( c) 100 v be (mv) 500 1100 1000 900 800 700 400 300 200 600 60 40 20 0 20 40 60 80 100 120 140 i c = 100 ma i c = 1 m a i c = 10 m a i c = 100 m a i c = 1 ma i c = 10 ma i c = 50 ma v ce = 3 v current i c 1 m a 200 v be (mv) 300 500 1000 1100 10 m a 1 ma 900 800 700 600 400 100 m a 10 ma v ce = 3 v 100 ma t = 125 c t = 0 c t = 25 c t = 70 c t = 55 c npn (large) current i c (ma) 0 v ce sat (mv) 200 500 450 400 350 300 150 100 50 250 0 102030405060708090100 npn (large) t = 125 c t = 0 c t = 25 c t = 55 c forced beta: b = 10 current i c 10 m a 300 v be sat (mv) 400 800 1100 100 m a 1 ma 10 ma 1000 900 600 500 700 100 ma t = 25 c t = 125 c t = 0 c t = 70 c t = 55 c npn (large) figure 27 figure 28 figure 29 figure 30
AS17XX semicustom bipolar array 126 astec semiconductor typical performance curves beta vs i e over temperature (C 55 c to 125 c) beta vs i e over temperature (C 55 c to 125 c) v ce sat vs i c v be sat vs temperature (with different i c ) figure 31 figure 32 figure 33 figure 34 current i e 10 m a 0 beta 40 100 140 200 260 300 100 m a 1 ma 10 ma 280 240 220 180 160 120 80 60 20 lateral pnp v ce = 3 v t = 70 c t = 125 c t = 55 c t = 25 c t = 0 c current i e 10 m a 0 beta 40 100 140 200 260 300 100 m a 1 ma 10 ma 280 240 220 180 160 120 80 60 20 vertical pnp v ce = 3 v t = 70 c t = 55 c t = 25 c t = 0 c t = 125 c current i c (ma) 0 v ce sat (mv) 400 1000 900 800 700 600 300 200 100 500 0 2 4 6 8 101214161820 t = 25 c forced beta: b = 1 lateral pnp temperature ( c) 0 v ce sat (mv) 400 1000 900 800 700 600 300 200 100 500 60 40 20 0 20 40 60 80 100 120 140 lateral pnp i c = 20 ma i c = 10 ma i c = 5 ma i c = 1 ma i c = 100 m a i c = 10 m a forced beta: b = 1
semicustom bipolar array AS17XX 127 astec semiconductor typical performance curves v be vs i c over temperature (C 55 c to 125 c) v be vs i c over temperature (C 55 c to 125 c) figure 35 figure 36 current i c 1 m a 300 v be (mv) 400 700 1400 1500 10 m a 1 ma 1100 1000 800 500 100 m a 10 ma 600 900 1200 1300 t = 0 c t = 25 c t = 70 c t = 55 c t = 125 c lateral pnp v ce = 3 v current i c 1 m a 300 v be sat (mv) 400 800 1100 10 m a 10 ma 1000 900 600 500 700 forced beta: b = 1 100 ma lateral pnp 100 m a t = 25 c t = 125 c t = 0 c t = 70 c t = 55 c the semicustom application the design considerations the designer should take advantage of the resis- tor and transistor matching available with ics and not rely on the absolute values of param- eters. if a certain emitter area is desired for current ratioing, several transistors can be connected in parallel to simulate this condition, or by using the desired emitter area of an npn power device (when breadboarding use the previous method). when using the double- collector pnp transistors, do not float one of the collectors; either tie them together or tie one to the substrate. floating one of the collectors will severely reduce the beta. there are several values and types of resistors available on the AS17XX semicustom array as outlined in the resistor summary. resistor summary 8 - pinch resistors ( ? 30 k w 50%, use at 5 v) 80 - base string resistors using full string lengths gives: 73 C 4 k w 7 C 1.5 k w using separate pieces of the strings gives: 67 C 500 w 63 C 1 k w 43 C 2 k w 30 C 4 k w note: do not try to use one resistor string for more than one resistor unless they are connected together in the circuit. additional components and their resistances are as follows: 13 - cross-unders (370 w for full length, and 190 w for half length) 6 - buses (at 10 w between connection points)
AS17XX semicustom bipolar array 128 astec semiconductor 5) high-frequency oscillations can, on rare oc- casions, occur in the integrated circuit when the breadboard did not show any tendency toward oscillation. this can be caused by the stray capacitances in the breadboard, which are larger than those associated with the ic and tend to stabilize potentially unstable cir- cuits. therefore, every effort should be made to minimize stray capacitances in the bread- board. this can be done by using dip sockets and soldered wire or printed circuit intercon- nects rather than the popular solderless plug- in breadboards which have up to 10 pf of pin-to-pin capacitance. breadboarding with kit parts all circuits should be breadboarded before being implemented on the semicustom array using as1700 kit parts, (which are transistor arrays made using the AS17XX semicustom array). this breadboard will simulate as accurately as pos- sible all stray effects and how the circuit will perform when implemented with the semicustom array. we recommend that standard carbon re- sistors be used to simulate the integrated resis- tors, or precision thin film resistors if accurate ratios are required. evaluating your breadboard after obtaining satisfactory performance from the breadboard, evaluate the effects of resistor, transistor and temperature variations. we recommend simulating the worst-case resis- tance variations (which is 30% globally and 1% for matching and ratioing) on the breadboard by substituting the appropriate values for all resis- tors. sensitivity to transistor parameter varia- tions can be seen by interchanging kit parts. we also recommend that the breadboard be tested over the full operating temperature range of the circuit. non-integratable components identify all non-integratable components such as inductors and capacitors. these will have to be supplied with external components. note that junction capacitors can be formed using transis- tors with collector and emitter tied together for limited capacitance values. minimizing stray effects (parasitics, currents, and capacitance) the following steps are recommended: 1) try to keep substrate currents as low as possible (under a few ma) to prevent isolation loss and cross-talk between adjacent compo- nents. if a component has a high substrate current, try to isolate it from the other compo- nents and keep it as close to the substrate bonding pad as possible. the substrate cur- rent should be measured for either each kit part or the whole breadboard (with all the substrates tied together) using a 10 w resistor connected to the most negative potential in the circuit. 2) do not saturate any pnp. if this is unavoid- able, limit the base current so that the sub- strate current in the kit part lead is kept low. this is because of the parasitic vertical pnp formed between the emitter, base and sub- strate in a lateral pnp will become active when the lateral pnp is saturated. 3) do not use any diode-connected pnp over about 500 m a to avoid the above mentioned parasitic pnp. 4) contact the n-layer (collector-plug) in the resistor-tubs to the most positive potential (this is for resistor-tub biasing and isolation, and is a concern only for the semicustom implementation of the circuit), and the substrate to the most negative potential in the circuit.
semicustom bipolar array AS17XX 129 astec semiconductor after testing is complete, make sure that the breadboard circuit is accurately reflected in the schematic by doing a thorough check to see if all modifications to the breadboard are included. layout options after thoroughly testing the breadboard, begin the layout process. there are three options for doing the layout: ? customer layout - you do the layout and provide astec with a completed layout sheet (at 500x - which astec will provide) ready for entry into our cad system. astec will review the layout for design rule violations and ad- vise you so that you can correct them yourself or elect to have astec fix them. ? vendor layout - you may assign astec the responsibility of the ic layout. ? customer supervised layout - you assign the layout implementation to astec but retain the responsibility for the final form and con- tent. basically you are subcontracting astec to do the ic layout under your direction. this option requires a great deal of communication between the customer and astec, but can yield the greatest control for the customer while reducing the layout time. layout guidelines we recommend that several copies of the layout on the data sheet be made to facilitate the layout process before working with the 500x layout sheet. the layout copies can be used to sketch various interconnect options, and work out any design problems that may be encountered be- cause of the layout process. functional blocks: we recommend that the circuit be broken down into functional blocks. the blocks are selected in such a way as to minimize the the number of interconnections with the other blocks. if the blocks are in sequence, the circuit can usually be divided so that only one or two connections are made between the blocks (other than power supply connections). block location: next, add up the number of devices and pads required by each block. then select an area of the chip for each block. there are a few considerations which must be kept in mind for the block placement. first, the selected area must contain the required number of com- ponents and pads. second, the various areas should be located so that interconnections be- tween them are as easy as possible. finally, the locations of the various pads to be bonded to pins and their relationships to each other and the blocks should be considered. bond wires should not cross each other. cross-unders & buses: cross-unders can be useful for small resistance values, but be careful of connections that can not tolerate cross-under resistance (see resistor summary), such as the base connections for a diode-biased current source, etc. to make sure that a connection can tolerate the cross-under resistance, insert the appropriate valued resistor in the breadboard and evaluate its effect on circuit performance. buses have low resistance and are valuable for connecting functional blocks together, and bus- ing power supply voltages. thermal considerations: if one or more com- ponents dissipate heat, they should be located away from other components that require close matching. the matched components should be placed together an equal distance from the thermal source. this way both of the matched components will be heated equally. total power dissipation in the circuit is a function of the package type and size. on average at least 500 mw can be dissipated without trouble. larger packages can dissipate more heat.
AS17XX semicustom bipolar array 130 astec semiconductor signal & common coupling: if high frequency signals are present which have large amplitude swings, these lines should be separated as much as possible with respect to their pin locations because of inductive or capacitive coupling be- tween their pins and bonding wires. another coupling problem arises when there are long metal lines. for example, if there is a com- mon ground line for both the input and output of an amplifier, the fluctuating current from the output could cause a voltage drop along the line that could effect the input. this coupling could cause distortion or oscillations. the solution to this problem is to run two separate ground lines to the ground pad. resistor ratioing: where matched resistor val- ues or precise ratios are required, identical resis- tor constructs and orientations should be used. identical resistors orientated 90 to each other may have different values due to directionally dependent fabrication and packaging tolerances. component interconnection: we recommend numbering the components on the circuit sche- matic and using these numbers on the layout. work on only one circuit block at a time and leave the block interconnections until all the blocks are finished. start the layout by selecting several components of a block and placing them on the layout; sketch their interconnections and work outward marking the schematic as you go. metal routing: the metal routing can be sketched on the layout sheet taking into account the de- sign rule considerations as follows: design rules: ? minimum metal width = 8 microns ? minimum spacing between metal traces = 8 microns ? current capacity of metal trace = 4 ma per micron of width ? metal line to pad (active) = 24 microns (note: metal resistance ? 0.02 w per square) the area around the outside of the chip has a metalized ring with numerous contacts to the substrate. the substrate must be connected to the most negative potential in the circuit. when laying out the circuit, the ground conductors should lead inward from the outer ring. there are several n-layer contacts for the different resistor tub areas that must be connected to the most positive potential in the circuit to maintain isolation. bonding pads: the rules for bonding pad lay- outs are very simple. you must be able to draw a straight line from a bonding pad to its pin without crossing any other wires, and the pads should be evenly spaced around the chip. the pin assignments are arbitrary, but they should be organized such that the pin numbers correspond to the pads in a counter-clockwise rotation around the chip, and not some random pattern that would cause bonding wires to cross each other. layout sheets (500x) are available upon re- quest for final layout, and are used to make the metal interconnect mask and check spacing rules. we recommend that the metal interconnect be done on a clear film over the layout sheet with erasable markers before making the final layout. this will allow for modifications to be made with a minimum amount of effort.
semicustom bipolar array AS17XX 131 astec semiconductor functional circuit blocks the following circuits are presented as a guide to assist in circuit design using the AS17XX semicustom array.complex circuit functions can be created from these elementry building blocks.these circuit blocks can be modified and improved to suit the designers needs in creating a complete system. current sources here are a few examples of pnp current sources; npn current sinks can easly be derived from the analog of these pnp examples. comparator input stages several comparator input stages are illustrated below. figure 2. simple pnp current source. has slower frequency response, and up to 15% tolerance error. i out = i in * (1 + 2/ b ) figure 3. widlar current source, moderate frequency response. i out = i in * (1 + 2/ b 2 ) figure 4. wilson current source, fast frequency response. i out = i in * (1 + 1/2 b 2 ) i in i out i in i out i in i out figure 5. simple npn type comparator. figure 6. simple npn type comparator input stage. figure 7. improved pnp type (good gnd sensing) comparator input stage. v cc v o v + v v cc v o v + v v cc v o v + v
AS17XX semicustom bipolar array 132 astec semiconductor figure 10. widlar band gap reference. d v be = v(r3) = v t * ln (a2/a1) v out = v be (q3) + (r2/r3) * d v be figure 8. zener diode v z = 7 v figure 9. v be multipled regulator. v out = v be * r2 /r1 v cc r 2 q 1 q 2 v o r 1 r 3 + v cc v o q 2 r 1 q 1 20x r 2 functional circuit blocks voltage regulators/references r 3 r 2 r 1 q 1 q 2 5x q 3 v 0 figure 11. brokaw band gap reference. d v be = v(r1) = v t * ln (a1/a2) v out = v be (q2) + v(r1) * 2 * r2/r1
semicustom bipolar array AS17XX 133 astec semiconductor flip-flop here are two examples of flip-flop circuits. functional circuit blocks reset set v cc q set v cc output load resistor reset figure 18. four layer latch flip-flop figure 17. fast, ecl flip-flop
AS17XX semicustom bipolar array 134 astec semiconductor functional circuit blocks trimming schemes there often arises the need to trim a parameter (i.e. voltage, current, oscillator frequency, offset null, etc.) to some particular value because of processing variations involved with wafer fabrication. we have developed two methods to accomplish this goal: 1) fuse link, where a fuse is blown to cause an open; and 2) zener zap, where a zener is taken well into breakdown until a short occurs. fuse link fuse links can be used similar to zeners for trimming, but the fuses must be located on a bonding pad inside the pad cut because a fuse wont blow if there is passivation over it. one possible trim scheme using fuse links is shown below. figure 13. figure 12. metal trace to circuit pad fuse link zener zap when using zener zap trim methods there are several points to keep in mind: the zener should be located near a pad, no cross-unders should be used to connect the zener with the pad, and the metal lines connecting the pad to the zener should be as thick as possible to allow the high current necessary to blow the zener. a few examples of the many possible trim schemes are shown in figure 14, figure 15 and figure 16. figure 14. simple trim setup with 8 trim steps. figure 16. parallel trim scheme with 8 trim steps. figure 15. trim scheme using only 3 pads to get 16 trim steps.
semicustom bipolar array AS17XX 135 astec semiconductor spice models: .model nmin npn; minimum npn + (is = 0.5fa bf = 200 nf = .995 vaf = 100 ikf = 20m ne = 1.45 + eg = 1.185 br = 5 nr = 0.98 var = 30 ikr = 2m xtb = 0.3 + rb = 270 rc = 60 re = 7 trb1 = 1.5m xti = 2.5 + cje = 450ff vje = 0.85 mje = 0.36 tf = 300ps + cjc = 200ff vjc = 0.57 mjc = 0.47 + cjs = 1.4pf vjs = 0.31 mjs = 0.35) .model plat lpnp; lateral pnp + (is = 0.9fa bf = 80 nf = 1 ikf = 60u ne = 1.5 + eg = 1.2 br = 30 nr = 0.98 ikr = 2m + rb = 30 rc = 200 re = 15 trc1 = 1.5m tre1 = 1.5m + vaf = 45 var = 30 + cje = 150ff vje = 0.57 mje = 0.47 tf = 30ns + cjc = 950ff vjc = 0.57 mjc = 0.47 xtb = 0.5 + cjs = 1.4pf vjs = 0.31 mjs = 0.35) .model pvert lpnp; vertical pnp + (is = 0.9fa bf = 100 nf = .995 vaf = 45 ikf = 1.5m + eg = 1.22 br = 30 nr = 0.98 var = 30 ikr = 2m ne = 1.25 + rb = 350 rc = 200 re = 300 trc1 = 1.5m tre1 = 1.5m + cje = 150ff vje = 0.57 mje = 0.47 tf = 30ns + cjc = 1.6pf vjc = 0.57 mjc = 0.47 xtb = 0.5) .model rbase res; base resistor + (r = 1 tc1 = 2.1m tc2 = 7u) .model rimp res; implant resistor + (r = 1.0 tc1 = 4m tc2 = 6u) .model rpinch res; pinch resistor + (r = 1.0 tc1 = 7m) .model dzener d; + (bv = 7.2v ibv = 1ua rs = 270 is = .1fa)
AS17XX semicustom bipolar array 136 astec semiconductor device layout cb e c cc bb bb c e b b e c c' rr r' r' f f' e e e e e e e e e e e e e e e e e e e e c c b b bbb pinch resistor with field contact minimum npn vertical pnp lateral pnp with split collector power (20x) npn component summary components available (single tile): small npn: 48 dual collector pnp: 21 vertical pnp 4 power npn 3 diffused resistors (total) ? 300 k w pinch resistors (3-terminal, 30k w )8 cross-unders 13 buses 6 resistor summary resistor summary: 8 - pinch resistors ( ? 30 k w 50%, use at 5 v) 80 - base string resistors using full string lengths gives: 73 - 4 k w 7 - 1.5 k w using separate pieces of the strings gives: 67 - 500 w 63 - 1 k w 43 - 2 k w 30 - 4 k w additional components and their resistances are as follows: 13 - cross-unders (370 w for full length, and 190 w for half length) 6 - buses (at 10 w between connection points) design rules design rules: ? minimum metal width = 8 microns ? minimum spacing between metal traces = 8 microns ? current capacity of metal trace = 4 ma per micron of width ? metal line to pad (active) = 24 microns (note: metal resistance ? 0.02 w per square)
semicustom bipolar array AS17XX 137 astec semiconductor device layout
AS17XX semicustom bipolar array 138 astec semiconductor notes

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